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MT90863 3V Rate Conversion Digital Switch
Data Sheet Features
* * * * * * * * * * * * * * 2,048 x 512 and 512 x 512 switching among backplane and local streams Rate conversion between 2.048, 4.096 and 8.192Mb/s Optional sub-rate switch configuration for 2.048 Mb/s streams Per-channel variable or constant throughput delay Compatible to HMVIP and H.100 specifications Automatic frame offset delay measurement Per-stream frame delay offset programming Per-channel message mode Per-channel direction control Per-channel high impedance output control Non-multiplexed microprocessor interface Connection memory block programming 3.3V local I/O with 5V tolerant inputs and TTL-compatible outputs IEEE-1149.1 (JTAG) Test Port Ordering Information MT90863AL MT90863AG 128 Pin MQFP 144 Pin BGA
February 2003
-40C to +85C
Description
The MT90863 Rate Conversion Switch provides switching capacities of 2,048 x 512 channels between backplane and local streams, and 512 x 512 channels for local streams. The connected serial inputs and outputs may have 32, 64 and 128 64kb/s channels per frame with data rates of 2.048Mb/s, 4.096Mb/s and 8.192Mb/s respectively. The MT90863 also offers a sub-rate switching configuration which allows 2-bit wide 16kb/s data channels to be switched within the device. The device has features (such as: message mode; input and output offset delay; direction control; and, high impedance output control) that are programmable on per-stream or per-channel basis.
Applications
* * * * Medium and large switching platforms CTI application Voice/data multiplexer Support ST-BUS, HMVIP and H.100 interfaces
ODE STio0/ FEi0 STio15/ FEi15 STio16/ FEi16 STio23/ FEi23 STio24 STio31 C16i F0i C4i/C8i Backplane Interface S/P & P/S Converter Multiple Buffer Data Memory (2,048 channels) VDD VSS
ODE
STo0 Output Mux Local Interface P/S Converter STo11 STo12 STo13 STo15 STi0 Local Interface S/P Converter STi11 STi12 STi13 STi15 RESET IC1 IC2
Internal Registers
Multiple Buffer Local Data Memory Connection (512 channels) Memory High/Low (512 locations) Multiple Buffer Data Memory (512 channels)
Timing Unit
Backplane Connection Memory (2,048 locations) Microprocessor Interface
Test Port
F0o C4o
DS CS R/W
A7-A0
DTA D15-D0
TMS TDi TDo
TCK TRST
Figure 1 - Functional Block Diagram
1
MT90863
VSS C4o F0o VSS C4i/C8i F0i VSS C16i VSS ST015 STo14 STo13 STo12 STo11 STo10 STo9 STo8 VDD VSS STo7 STo6 STo5 STo4 STo3 STo2 STo1 STo0 ODE VSS VDD STi15 STi14
Data Sheet
95
93
91
89
87
85
83
81
79
77
75
73
71
69
67
65 63
VDD STio0/FEi0 STio1/FEi1 STio2/FEi2 STio3/FEi3 STio4/FEi4 STio5/FEi5 STio6/FEi6 STio7/FEi7 VSS VDD STio8/FEi8 STio9/FEi9 STio10/FEi10 STio11/FEi11 STio12/FEi12 STio13/FEi13 STio14/FEi14 STio15/FEi15 VSS VDD STio16/FEi16 STio17/FEi17 STio18/FEi18 STio19/FEi19 STio20/FEi20 STio21/FEi21 STio22/FEi22 STio23/FEi23 VSS VDD STio24
97 99 61 101 59 103 57 105 55 107 53 109 111 113 115 45 117 43 119 41 121 39 123 37 125 35 127 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
128 Pin MQFP 28mm x 28mm Pin Pitch 0.80mm
51 49 47
STi13 STi12 STi11 STi10 STi9 STi8 STi7 STi6 STi5 STi4 STi3 STi2 STi1 STi0 VDD VSS DTA D15 D14 D13 D12 D11 D10 D9 D8 VSS D7 D6 D5 D4 D3 D2
2
STio25 STio26 STio27 STio28 STio29 STio30 STio31 VSS TMS TDi TDo TCK TRST IC1 RESET IC2 VSS A0 A1 A2 A3 A4 A5 A6 A7 DS R/W CS VSS VDD D0 D1
Figure 2 - MQFP Pin Connections
Zarlink Semiconductor Inc.
Data Sheet
MT90863
1 2 3 4 5 6 7 8 9 10 11 12 13
1 A B C
STio26 STio24 STio22 STio19 STio17 STio15 STio14 STio11 STio8 STio6 STio4 STio3
F0o
STio29 STio25 STio23 STio20 STio18 STio16 STio13 STio10 STio7 STio5 STio2 STio1 C4i/C8i
TMS STio28 STio27 STio21 D TDi E TCK F RESET TRST G A0 H A1 J A5 K L CS M D0 N D1 D3 D6 D9 D2 D4 D8 R/W VSS D5 A7 A4 DS A6 VDD VSS VDD A2 A3 VDD VSS IC2 VSS IC1 VDD TDo VSS VSS STio31 STio30 VSS
VDD VDD
VSS STio12 STio9 VSS VDD VSS
VDD VDD
VSS VSS
STio0 F0i
C4o STo15 C16i STo13
VDD STo14 STo12 STo11 VSS VSS STo10 STo9 VDD STo4 VSS VDD STo8 STo6 STo3 STo1 STo7 STo5 STo2 STo0
TOP VIEW
VDD VSS VSS
VSS D7 D10 D13
VDD D11 D12 D14
VSS VSS D15 DTA
VDD VDD STi1 STi0
VSS STi6 STi4 STi2
VDD STi8 STi7 STi3
STi12 STi15 ODE STi10 STi13 STi14 STi5 STi9 STi11
1
- A1 corner is identified by metallized markings. 23mm x 23mm Ball Pitch 1.5mm
Figure 3 - BGA Pin Connections
Zarlink Semiconductor Inc.
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MT90863
Pin Description
128 MQFP Pin# 144 BGA Pin# Name VDD +3.3 Volt Power Supply Description
Data Sheet
30,50,67, C5,C9,D5,D7, 79,97,107, D9,E10,F4,G10 117,127 ,G11,H4, K3,K4,K6,K8 K10,K11,L8 8,17,29,39, C6,C10,D4,D6, 49,68,78,8 D8,D10,E3,E4, 8,90,93,96, F10,F11,G2, 106, G4,H10,J4, 116,126 J10,J11,K5 K7,K9,L3,L7 89 91 D12 D11
Vss
Ground
C16i F0i
Master Clock (5V Tolerant Input): Serial clock for shifting data in/out on the serial streams. This pin accepts a 16.384 MHz clock. Master Frame Pulse (5V Tolerant Input): In ST-BUS mode, this input accepts a 61ns wide negative frame pulse. In CT Bus mode, it accepts a 122ns wide negative frame pulse. In HMVIP mode, it accepts a 244ns wide negative frame pulse. HMVIP/CT Bus Clock (5V Tolerant Input): When HMVIP mode is enabled, this pin accepts a 4.096MHz clock for HMVIP frame pulse alignment. When CT Bus mode is enabled, it accepts a 8.192MHz clock for CT frame pulse alignment. Frame Pulse (5V Tolerant Output): A 244ns wide negative frame pulse that is phase locked to the master frame pulse (F0i). C4 Clock (5V Tolerant Output): A 4.096MHz clock that is phase locked to the master clock (C16i).
92
B13
C4i/C8i
94 95 98-105, 108-115
A13 C12 C11, B12, B11, A12, A11, B10, A10, B9, A9, C8, B8, A8, C7, B7, A7, A6,
F0o C4o
STio0 - 15 Serial Input Streams 0 to 15 / Frame Evaluation Inputs 0 to 15 (5V FEi0 - 15 Tolerant I/O). In 2Mb/s and HMVIP modes, these pins accept serial TDM data streams at 2.048 Mb/s with 32 channels per stream. In 4Mb/s or 8Mb/s mode, these pins accept serial TDM data streams at 4.096 or 8.192 Mb/s with 64 or 128 channels per stream respectively. In Frame Evaluation Mode (FEM), they are frame evaluation inputs.
118-125
B6, A5, B5, A4, STio16 - 23 Serial Input Streams 16 to 23 (5V Tolerant I/O). In 2Mb/s or 4Mb/s B4, C4, A3, B3 FEi16 - 23 mode, these pins accept serial TDM data streams at 2.048 or 4.096 Mb/s with 32 or 64 channels per stream respectively. In HMVIP mode, these pins have a data rate of 8.192Mb/s with 128 channels per stream. In Frame Evaluation Mode (FEM), they are frame evaluation inputs. A2, B2, A1, C3, STio24 - 31 Serial Input Streams 24 to 31 (5V Tolerant I/O). These pins are only C2, B1, D3, D2 used for 2Mb/s or 4Mb/s mode. They accept serial TDM data streams at 2.048 or 4.096 Mb/s with 32 or 64 channels per stream respectively. C1 D1 TMS TDi Test Mode Select (3.3V Input with internal pull-up): JTAG signal that controls the state transitions of the TAP controller. Test Serial Data In (3.3V Input with internal pull-up): JTAG serial test instructions and data are shifted in on this pin.
128, 1-7 9 10
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Zarlink Semiconductor Inc.
Data Sheet Pin Description (continued)
128 MQFP Pin# 11 144 BGA Pin# E2 Name TDo Description
MT90863
Test Serial Data Out (3.3V Output): JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in a high impedance state when JTAG scan is not enabled. Test Clock (5V Tolerant Input): Provides the clock to the JTAG test logic. Test Reset (3.3 V Input with internal pull-up): Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up, or held low continuously, to ensure that the MT90863 is in the normal operation mode. Internal Connection 1 (3.3V Input with internal pull-down): Connect to VSS for normal operation. Device Reset (5V Tolerant Input): This input (active LOW) puts the MT90863 in its reset state. This clears the device's internal counters and registers. Internal Connection 2 (3.3V Input): Connect to VSS for normal operation. Address 0 - 7 (5V Tolerant Input): These lines provide the A0 to A7 address lines to the internal memories. Data Strobe (5V Tolerant Input): This active low input works in conjunction with CS to enable the read and write operations. Read/Write (5V Tolerant Input): This input controls the direction of the data bus lines (D0-D15) during a microprocessor access. Chip Select (5V Tolerant Input): Active low input used by a microprocessor to activate the microprocessor port. Data Bus 0 -15 (5V Tolerant I/O): These pins form the 16-bit data bus of the microprocessor port.
12 13
E1 F2
TCK TRST
14 15
F3 F1
IC1 RESET
16 18-25 26 27 28 31-38, 40-47
G3 G1, H1, H2, H3, J2, J1,J3, K1 K2 L2 L1 M1, N1, M2, N2, M3, L4, N3, L5, M4, N4, M5, L6, M6, N5, N6, M7, N7
IC2 A0 - A7 DS R/W CS D0 - 7, D8 - D15
48
DTA
Data Transfer Acknowledgment (5V Tolerant Three-state Output): This active low output indicates that a data bus transfer is complete. A pull-up resistor is required to hold a HIGH level when the pin is tri-stated. Serial Input Streams 0 to 3 (5V Tolerant Inputs): In 2Mb/s or Subrate Switching mode, these inputs accept data rates of 2.048 Mb/s with 32 channels per stream. In 8Mb/s mode, these inputs accept data rates of 8.192 Mb/s with 128 channels per stream. Serial Input Streams 4 to 11 (5V Tolerant Inputs): In 2Mb/s or Sub-rate Switching mode, these inputs accept data rates of 2.048Mb/s with 32 channels per stream.
51-54
N8, M8, N9, N10
STi0 - 3
55-62
M9, N11, L9, M10, L10, N12, M11, N13
STi4 - 11
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MT90863
Pin Description (continued)
128 MQFP Pin# 63 144 BGA Pin# L11 Name STi12 Description
Data Sheet
Serial Input Streams 12 (5V Tolerant Input): In 2Mb/s mode, this input accepts data rate of 2.048Mb/s with 32 channels per stream respectively. In Sub-rate Switching mode, this pin accepts 2.048Mb/s with 128 channels per stream for Sub-rate switching application.
64-66
M12, M13, L12
STi13 - 15 Serial Input Streams 13 to 15 (5V Tolerant Inputs): In 2Mb/s mode, these inputs accept a data rate of 2.048Mb/s with 32 channels per stream. ODE Output Drive Enable (5V Tolerant Input): This is the output enable control for the STo0 to STo15 serial outputs and STio0 to STio31 serial bidirectional outputs. Serial Output Streams 0 to 3 (5V Tolerant Three-state Outputs): In 2Mb/s or Sub-rate Switching mode, these outputs have data rates of 2.048 Mb/s with 32 channels per stream respectively. In 8Mb/s mode, these outputs have data rates of 8.192 Mb/s with 128 channels per stream
69
L13
70-73
K13, K12, J13, J12
STo0 - 3
74-77, 80-83 84
H11, H13, H12, G13, G12, F13, F12, E13 E12
STo4 - 7, Serial Output Streams 4 to 11 (5V Tolerant Three-state Outputs): STo8 - 11 In 2Mb/s or Sub-rate Switching mode, these outputs have data rates of 2.048Mb/s with 32 channels per stream STo12 Serial Output Streams 12 (5V Tolerant Three-state Output): In 2Mb/s mode, this output has data rate of 2.048Mb/s with 32 channels per stream. In Sub-rate Switching mode, this pin has data rate of 2.048Mb/s with 128 channels per stream for Sub-rate switching application.
85-87
D13, E11, C13
STo13 - 15 Serial Output Streams 13 to 15 (5V Tolerant Three-state Outputs): In 2Mb/s mode, these outputs have a data rate of 2.048Mb/s with 32 channels per stream.
1.0
Device Overview
The Rate conversion Switch (MT90863) can switch up to 2,048 x 512 channels while also providing a rate conversion capability. It is designed to switch 64 kb/s PCM or N X 64 kb/s data between the backplane and local interfaces. When the device is in the sub-rate switching mode, 2-bit wide 16 kb/s data channels can be switched within the device. The device maintains frame integrity in data applications and minimum throughput delay for voice application on a per channel basis. The backplane interface can operate at 2.048, 4.096 or 8.192 Mb/s, arranged in 125s wide frames that contain 32, 64 or 128 channels, respectively. A built-in rate conversion circuit allows users to interface between backplane interface and the local interface which operates at 2.048 Mb/s or 8.192 Mb/s. By using Mitel's message mode capability, the microprocessor can access input and output time-slots on a per channel basis. This feature is useful for transferring control and status information for external circuits or other STBus devices. The frame offset calibration function allows users to measure the frame offset delay for streams STio0 to STio23. The offset calibration is activated by a frame evaluation bit in the frame evaluation register. The evaluation result is stored in the frame evaluation registers and can be used to program the input offset delay for individual streams using internal frame input offset registers.
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Data Sheet 2.0 Functional Description
MT90863
A functional Block Diagram of the MT90863 is shown in Figure 1. One end of the MT90863 is used to interface with backplane applications, such as HMVIP or H.100 environments, while the other end supports the local switching environments.
2.1
Frame Alignment Timing
The Device Mode Selection (DMS) register allows users to select three different frame alignment timing modes. In ST-BUS modes, the master clock (C16i) is always at 16.384 MHz. The frame pulse (F0i) input accepts a negative frame pulse at 8kHz. The frame pulse goes low at the frame boundary for 61ns. The frame pulse output F0o provides a 244ns wide negative frame pulse and the C4o output provides a 4.094MHz clock. These two signals are used to support local switching applications. See Figure 4 for the ST-BUS timings. In CT Bus mode, the C4i/C8i pin accepts 8.192MHz clock for the CT Bus frame pulse alignment. The F0i is the CT bus frame pulse input. The CT frame pulse goes low at the frame boundary for 122ns. See Figure 5 for the CT Bus timing. In HMVIP mode, the C4i/C8i pin accepts 4.096MHz clock for the HMVIP frame pulse alignment. The F0i is the HMVIP frame pulse input. The HMVIP frame pulse goes low at the frame boundary for 244ns. See Figure 6 for the HMVIP timing. Table 1 - describes the input timing requirements for ST-BUS, CT Bus and HMVIP modes.
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MT90863
3.0 Switching Configuration
Data Sheet
The device has four operation modes for the backplane interface and three operation modes for the local interface. These modes can be programmed via the Device Mode Selection (DMS) register. Mode selections between the backplane and local interfaces are independent. See Table 2 and Table 3 for the selection of various operation modes via the programming of the DMS register.
3.1
Backplane Interface
The backplane interface can be programmed to accept data streams of 2Mb/s, 4Mb/s or 8Mb/s. When 2Mb/s mode is enabled, STio0 to STio31 have a data rate of 2.048Mb/s. When 4Mb/s mode is enabled, STio0 to STio31 have a data rate of 4.096Mb/s. When 8Mb/s mode is enabled, STio0 to STio15 have a data rate of 8.192Mb/s. When HMVIP mode is enabled, STio0 to STio15 have a data rate of 2.048Mb/s and STio16 to STio23 have a data rate of 8.192Mb/s. Table 2 describes the data rates and mode selection for the backplane interface.
F0i
C16i F0o
C4o STio 0 - 15 STi/STo 0 - 3 (8Mb/s mode)
Channel 0 1 0 7 6 5 4 3 2 1 0 6 5 Channel 127 4 3 2 1 0 7
Channel 0
Channel 63 5 4 3 2 1 0 7
STio 0 - 31 (4Mb/s mode)
0
7
6
STio 0 - 31 STi/STo 0 - 15 (2Mb/s mode) STi12/STo12 (Sub-rate Switching)
Channel 0 0 7 6 1
Channel 31 0 7
Channel 0 0 1 0 1
Channel 127 0 Bit 1
Figure 4 - ST-BUS Timing for 2, 4 and 8 Mb/s Data Streams
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Data Sheet
MT90863
F0i (CT_FRAME) C4i/C8i (8.192MHz) C16i
F0o
C4o
Channel 0 1 0 7 6 5 4 3 2 1 0 6 5 Channel 127 4 3 2 1 0 7
STio 0 - 15 STi/STo 0 - 3 (8Mb/s mode) STio 0 - 31 (4Mb/s mode)
Channel 0 0 7 6 5 4 3
Channel 63 2 1 0 7
STio 0 - 31 STi/STo 0 - 15 (2Mb/s mode) STi12/STo12 (Sub-rate Switching)
Channel 0 0 7 6 1
Channel 31 0 7
Channel 0 0 1 0 1
Channel 127 0 Bit 1
Figure 5 - CT Bus Mode Timing for 2, 4 and 8 Mb/s Data Streams
F0i (HMVIP Frame) C4i/C8i (4.096MHz) C16i
F0o
C4o Channel 0 STio 0 - 15 STi/STo 0 - 15 (2Mb/s mode) STio 16 - 23 (8Mb/s mode) 1 0 7 Channel 0 0 7 6 5 4 3 2 1 0 6 5 6 1 Channel 127 4 3 2 1 0 7 Channel 31 0 7
Channel 0 STi12/STo12 (Sub-rate Switching) 0 1 0 1
Channel 127 0 Bit 1
Figure 6 - HMVIP Mode Timing for 2 and 8 Mb/s Data Streams
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MT90863
3.2 Local Interface
Data Sheet
Three operation modes, 2Mb/s, 8Mb/s and Sub-rate Switching mode, can be selected for the local interface. When 2Mb/s mode is selected, STi0 to STi15 and STo0 to STo15 have a 2.048Mb/s data rate. When 8Mb/s mode is selected, STi0 to STi3 and STo0 to STo3 have an 8.192Mb/s data rate. When Sub-rate Switching mode is selected, STi0 to STi11 and STo0 to STo11 have 2.048Mb/s data with 64kb/s data channels and STi12 and STo12 have a 2.048Mb/s data rate with 16kb/s data channels. Table 3 describes the data rates and mode selection for the local interface.
3.3
Input Frame Offset Selection
Input frame offset selection allows the channel alignment of individual backplane input streams, that operate at 8.192Mb/s (STio0-23), to be shifted against the input frame pulse (F0i). This feature compensates for the variable path delays caused by serial backplanes of variable length. Such delays can be occur in large centralized and distributed switching systems. Each backplane input stream can have its own delay offset value by programming the input delay offset registers (DOS0 to DOS5). Possible adjustment can range up to +4 master clock (C16i) periods forward with resolution of half master clock period. See Table 10 and Table 11, and Figure 9,Figure 9 - for frame input delay offset programming.
3.4
Output Advance Offset Selection
The MT90863 allows users to advance individual backplane output streams which operate at 8.192Mb/s (STio0-23) by half a master clock (C16i) cycle. This feature is useful in compensating for variable output delays caused by various output loading conditions. The frame output offset registers (FOR0 & FOR1) control the output offset delays for each backplane output stream via the OFn bit programming. Table 12 and Figure 10 detail frame output offset programming.
3.5
Serial Input Frame Alignment Evaluation
The MT90863 provides the frame evaluation inputs, FEi0 to FEi23, to determine different data input delays with respect to the frame pulse F0i. By using the frame evaluation input select bits (FE0 to FE4) of the frame alignment register (FAR), users can select one of the twenty-four frame evaluation inputs for the frame alignment measurement. A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the evaluation starts when the SFE bit in the Internal Mode Selection (IMS) register is changed from low to high. One frame later, the complete frame evaluation (CFE) bit of the frame alignment register changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 9 of the FAR register. The SFE bit must be set to zero before a new measurement cycle is started. Timing Signals F0i Width C4i/C8i C16i F0o Width C4o ST-BUS Mode 61ns Not Required CT Bus Mode 122ns 8.192MHz 16.384MHz 244ns 4.096MHz Table 1 - Timing Signals Requirements for Various Operation Modes HMVIP Mode 244ns 4.096MHz
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Data Sheet
MT90863
DMS Register Bits BMS2 0 0 0 0 1 1 1 BMS1 0 0 1 1 0 0 1 BMS0 0 1 0 1 0 1 0
Modes 2Mb/s, ST-BUS Mode 2Mb/s, CT Bus Mode 4Mb/s, ST-BUS Mode 4Mb/s, CT Bus Mode 8Mb/s, ST-BUS Mode 8Mb/s, CT Bus Mode HMVIP Mode
Backplane Interface STio0 - 31 STio0 - 31 STio0 - 31 STio0 - 31 STio0 - 15 STio16 - 31 STio0 - 15 STio16 - 31 STio0 - 15 STio16 - 23 STio24 - 31
Data Rate 2.048 Mb/s 2.048 Mb/s 4.096 Mb/s 4.096 Mb/s 8.192 Mb/s Not available 8.192 Mb/s Not available 2.048 Mb/s 8.192 Mb/s Not available
Table 2 - Mode Selection for Backplane interface DMS Register Bits LMS1 0 0 LMS0 0 1
Modes 2Mb/s Mode Sub-Rate Switching Mode
Local Interface STi0 - 15 STo0 - 15 STi0 - 11 STi12 STi13 - 15 STo0 - 11 STo12 STo13 - 15 2.048 Mb/s 2.048 Mb/s 2.048 Mb/s
Data Rate
Sub-rate Switching Input Stream at 2.048 Mb/s Not available 2.048 Mb/s Sub-rate Switching Output Stream at 2.048Mb/s Not available 8.192 Mb/s Not available 8.192 Mb/s Not available
1
0
8Mb/s Mode
STi0 - 3 STi4 - 15 STo0 - 3 STo4 - 15
Table 3 - Mode Selection for Local Interface The falling edge of the frame measurement signal (FEi) is evaluated against the falling edge of the frame pulse (F0i). Table 8 and Figure 8 describe the frame alignment register.
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MT90863
3.6 Memory Block Programming
Data Sheet
The MT90863 has two connection memories: the backplane connection memory and the local connection memory. The local connection memory is partitioned into high and low parts. The IMS register provides users with the capability of initializing the local connection memory low and the backplane connection memory in two frames. Bit 11 to bit 13 of every backplane connection memory location will be programmed with the pattern stored in bit 7 to bit 9 of the IMS register. Bit 12 to 15 of every local connection memory low location will be programmed with the pattern stored in bits 3 to 6 of the IMS register. The block programming mode is enabled by setting the memory block program (MBP) bit of the control register high. When the block programming enable (BPE) bit of the IMS register is set to high, the block programming data will be loaded into bits 11 to 13 of every backplane connection memory and bits 12 to 15 of every local connection memory low. The other connection memory bits are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to zero. See Figure 7 for the connection memory contents when the device is in block programming mode.
4.0
Delay Through the MT90863
The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum delay between input and output data. In wideband data applications, select constant throughput delay to maintain the frame integrity of the information through the switch. The delay through the device varies according to the type of throughput delay selected in the LV/C and BV/C bits of the local and backplane connection memory as described in Table 16 and Table 19.
4.1
Variable Delay Mode (LV/C or BV/C bit = 0)
The delay in this mode is dependent only on the combination of source and destination channels and is independent of input and output streams.
4.2
Constant Delay Mode (LV/C bit or BV/C= 1)
In this mode a multiple data memory buffer is used to maintain frame integrity in all switching configurations.
5.0
Microprocessor Interface
The MT90863 provides a parallel microprocessor interface for non-multiplexed bus structures. This interface is compatible with Motorola non-multiplexed buses. The required microprocessor signals are the 16-bit data bus (D0D15), 8-bit address bus (A0-A7) and 4 control lines (CS, DS, R/W and DTA). See Figure 16 - Figure 16 for Motorola non-multiplexed bus timing. The MT90863 microprocessor port provides access to the internal registers, connection and data memories. All locations provide read/write access except for the Data Memory and the Data Read Register which are read only.
5.1
Memory Mapping
The address bus on the microprocessor interface selects the internal registers and memories of the MT90863. If the A7 address input is low, then the registers are addressed by A6 to A0 as shown in Table 4. If the A7 is high, the remaining address input lines are used to select the serial input or output data streams corresponding to the subsection of memory positions. For data memory reads, the serial inputs are selected. For connection memory writes, the serial outputs are selected. The control, device mode selection and internal mode selection registers control all the major functions of the device. The device mode selection register and internal mode selection register should be programmed
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Data Sheet
MT90863
immediately after system power-up to establish the desired switching configuration as explained in the Frame Alignment Timing and Switching Configurations sections. The control register is used to control the switching operations in the MT90863. It selects the internal memory locations that specify the input and output channels selected for switching. Control register data consists of: the memory block programming bit (MBP): the memory select bits (MS0-2); and, the stream address bits (STA0-4). The memory block programming bit allows users to program the entire connection memory block, (see Memory Block Programming section). The memory select bits control the selection of the connection memory or the data memory. The stream address bits define an internal memory subsections corresponding to serial input or serial output streams.
15
0
14
0
13
BBPD 2
12
BBPD 1
11
BBPD 0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Backplane Connection Memory (BCM) 15
LBPD 3
14
LBPD 2
13
LBPD 1
12
LBPD 0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Local Connection Memory Low (LCML) 15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Local Connection Memory High (LCMH)
Figure 7 - Block Programming Data in the Connection Memories A7 (Note 1) 0 0 0 0 0 0 0 0 0 0 0 0 0
A6 0 0 0 0 0 0 0 0 0 0 0 0 0
A5 0 0 0 0 0 0 0 0 0 0 0 0 0
A4 0 0 0 0 0 0 0 0 0 0 0 0 0
A3 0 0 0 0 0 0 0 0 1 1 1 1 1
A2 0 0 0 0 1 1 1 1 0 0 0 0 1
A1 0 0 1 1 0 0 1 1 0 0 1 1 0
A0 0 1 0 1 0 1 0 1 0 1 0 1 0
Location Control Register, CR Device Mode Selection Register, DMS Internal Mode Selection Register, IMS Frame Alignment Register, FAR Input Offset Selection Register 0, DOS0 Input Offset Selection Register 1, DOS1 Input Offset Selection Register 2, DOS2 Input Offset Selection Register 3, DOS3 Input Offset Selection Register 4, DOS4 Input Offset Selection Register 5, DOS5 Frame Output Offset Register, FOR0 Frame Output Offset Register, FOR1 Address Buffer Register, ABR
Table 4 - Address Memory Map
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MT90863
A7 (Note 1) 0 0 1 1 1 1 1 1 1 . 1 1 A6 0 0 0 0 0 0 0 0 0 . 1 1 A5 0 0 0 0 0 0 0 1 1 . 1 1 A4 0 0 0 0 . 1 1 0 0 . 1 1 A3 1 1 0 0 . 1 1 0 0 . 1 1 A2 1 1 0 0 . 1 1 0 0 . 1 1 A1 0 1 0 0 . 1 1 0 0 . 1 1 A0 1 0 0 1 . 0 1 0 1 . 0 1 Location Data Write Register, DWR Data Read Register, DRR Ch 0 Ch 1 . Ch 30 Ch 31 Ch 32 Ch 33 . Ch 126 Ch 127
Data Sheet
(Note
2)
(Note
3)
Notes: 1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers. 2. Channels 0 to 31 are used when serial stream is at 2Mb/s. 3. Channels 0 to 127 are used when serial stream is at 8Mb/s
Table 4 - Address Memory Map (continued) The data in the DMS register consists of the local and backplane mode selection bits (LMS0-1 and BMS0-2) to enable various switching modes for local and backplane interfaces respectively. The data in the IMS register consists of block programming bits (LBPD0-3 and BBPD0-2), block programming enable bit (BPE), output standby bit (OSB) and start frame evaluation bit (SFE). The block programming enable bit allows users to program the entire backplane and local connection memories, (see Memory Block Programming section). If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all ST-BUS output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and all ST-BUS output drivers are enabled. See Table 5 for the output high impedance control.
5.2
Address Buffer Mode
The implementation of the address buffer, data read and data write registers allows faster memory read/write operation for the microprocessor port. See Table 6 and following for bit assignments. The address buffer mode is controlled by the AB bit in the control register. The targeted memory for data read/write is selected by the MS0-2 bits in the control register. The data write register (DWR) contains the data to be transferred to the memory. The data read register (DRR) contains the data transferred from the memory. The address buffer register (ABR) allow users to specify the read or write address by programming the stream address bits (SA0-4) and the channel address bits (CA0-6). Data transfer from/to the memory is controlled by the read/write select bits (RS, WS). The complete data access (CDA) bit indicates the completion of data transfer between the memory and DWR or DRR register.
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Data Sheet
5.3 Write Operation Using Address Buffer Mode
MT90863
Enable the address buffer mode by setting the AB bit from low to high. Program the DWR register with data to be transferred to memory. Load the ABR register with proper channel and stream information. Change the WS bit in the ABR register from low to high to initiate the data transfer from the DWR register to the memory. After several master clock cycles, the CDA bit in the ABR register changes from low to high to signal the completion of data transfer and resets the WS bit to low. Repeat the above steps for subsequent memory write operations. Disable the address buffer write operation by setting the AB bit to low.
5.4
Read Operation Using Address Buffer Mode
Enable the address buffer mode by setting the AB bit from low to high. Program the ABR register with proper channel and stream information. Change the RS bit in the ABR register from low to high to initiate the data transfer from the memory to the DRR register. After several master clock cycles, the CDA bit in the ABR register changes from low to high to signal the completion of data transfer and resets the RS bit to low. Read the DRR register to obtain the data transferred from the memory. Repeat the above steps for subsequent memory read operations. Disable the address buffer read operation by setting the AB bit to low.
5.5
Backplane Connection Memory Control
The backplane connection memory controls the switching configuration of the backplane interface. Locations in the backplane connection memory are associated with particular STio output streams. The BV/C (Variable/Constant Delay) bit of each backplane connection memory location allows the per-channel selection between variable and constant throughput delay modes for all STio channels. In message mode, the message channel (BMC) bit of the backplane connection memory enables (if high) an associated STio output channel. If the BMC bit is low, the contents of the backplane connection memory stream address bit (BSAB) and channel address bit (BCAB) defines the source information (stream and channel) of the time-slot that will be switched to the STio streams. When message mode is enabled, only the lower half (8 least significant bits) of the backplane connection memory is transferred to the STio pins. OSB bit in IMS register Don't Care 0 1 Don't care STio0-31 Output Driver Status Per Channel High Impedance High Impedance Enable Enable STo0-15 Output Driver Status Per Channel High Impedance High Impedance Enable Enable
ODE pin Don't Care 0 0 1
DC bit in Backplane CM 0 Don't care 1 1
OE bit in Local CM 0 Don't care 1 1
Table 5 - Output High Impedance Control
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MT90863
Read/Write Address: 15 14 13 12
0 0 0 0
Data Sheet
11
0
00H, Reset Value: 10 9 8
AB CT MBP
7
0000H. 6
MS1
5
MS0
4
3
2
STA2
1
STA1
0
STA0
MS2
STA4 STA3
Bit 15-11 10
Name Unused AB Must be zero for normal operation.
Description
Address Buffer. When 1, enables the address buffer, data write and data read registers for accessing various memory locations for fast microport access. When 0, disables the address buffer, data write and data read registers. Channel Tri-state. When 1, the last bit of each output channel is tri-stated for -22ns against the channel boundary. When 0, the last bit of each channel is not tri-stated. Memory Block Program. When 1, the connection memory block programming feature is ready for the programming of bit 11 to 13 for backplane connection memory, bit 12 to 15 for local connection memory low. When 0, this feature is disabled. Memory Select Bits. These three bits are used to select connection and data memory functions as follows: MS2-0 Memory Selection 000 Local Connection Memory Low Read/Write, 001 Local Connection Memory High Read/Write, 010 Backplane Connection Memory Read/Write, 011 Local Data Memory Read, 100 Backplane Data Memory Read, Stream Address Bits. The binary value expressed by these bits refers to the input or output data stream, which corresponds to the subsection of memory made accessible for subsequent operations. (STA4 = MSB, STA0 = LSB)
9 8
CT MBP
7-5
MS2-0
4-0
STA4-0
Table 6 - Control (CR) Register Bits Read/Write Address: 15 14 13 12
0 0 0 0
11
0
01H, Reset Value: 10 9 8
0 0 0
7
0
0000H. 6
0
5
0
4
LMS1
3
2
1
0
LMS0 BMS2 BMS1 BMS0
Bit 15 - 5 4-3
Name unused LMS Reserved
Description
Local Mode Selection Bit. The binary value expressed by these bits refers to the following backplane interface switching modes: Local Switching Mode LMS1-0 00 2Mb/s ST-BUS Mode 01 2Mb/s Sub-rate Switching Mode 10 8Mb/s ST-Bus Mode
Table 7 - Device Mode Selection (DMS) Register Bits
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Zarlink Semiconductor Inc.
Data Sheet
Read/Write Address: 15 14 13 12
0 0 0 0
MT90863
01H, Reset Value: 10 9 8
0 0 0
11
0
7
0
0000H. 6
0
5
0
4
LMS1
3
2
1
0
LMS0 BMS2 BMS1 BMS0
Bit 2-0
Name BMS2-0
Description Backplane Mode Selection Bits. The binary value expressed by these bits refers to the following backplane interface switching modes: Backplane Switching Mode BMS2-0 000 2Mb/s ST-BUS Mode 001 2Mb/s CT Bus Mode 010 4Mb/s ST-BUS Mode 011 4Mb/s CT Bus Mode 100 8Mb/s ST-BUS Mode 101 8Mb/s CT Bus Mode 110 HMVIP Mode
Note: Please refer to Table 1 for Timing Signal Requirements
Table 7 - Device Mode Selection (DMS) Register Bits (continued)
5.6
Local Connection Memory Control
The local connection memory controls the local interface switching configuration. Local connection memory is split into high and low parts. Locations in local connection memory are associated with particular STo output streams. The L/B (Local/Backplane Select) bit of each local connection memory location allows per-channel selection of source streams from local or backplane interface. The LV/C (Variable/Constant Delay) bit of each local connection memory location allows the per-channel selection between variable and constant throughput delay modes for all STo channels. In message mode, the local connection memory message channel (LMC) bit enables (if high) an associated STo output channel. If the LMC bit is low, the contents of the stream address bit (LSAB) and the channel address bit (LCAB) of the local connection memory defines the source information (stream and channel) of the time-slot that will be switched to the STo streams. When message mode is enabled, only the lower half (8 least significant bits) of the local connection memory low bits are transferred to the STo pins. When sub-rate switching is enabled, the LSR0-1 bits in the local connection memory high define which bit position contains the sub-rate data.
5.7
DTA Data Transfer Acknowledgment Pin
The DTA pin is driven LOW by internal logic to indicate (to the CPU) that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then switches to the high-impedance state. If a short or signal contention prevents the DTA pin from reaching a valid logic HIGH, it will continue to drive for approximately 15nsec before switching to the high-impedance state.
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MT90863
6.0 Initialization of the MT90863
Data Sheet
During power up, the TRST pin should be pulsed low, or held low continuously, to ensure that the MT90863 is in the normal operation mode. A 5K pull-down resistor can be connected to this pin so that the device will not enter the JTAG test mode during power up. After power up, the contents of the connection memory can be in any state. The ODE pin should be held low after power up to keep all serial outputs in a high impedance state until the microprocessor has initialized the switching matrix. This procedure prevents two serial outputs from driving the same stream simultaneously. During the microprocessor initialization routine, the microprocessor should program the desired active paths through the switch. The memory block programming feature can also be used to quickly initialize the DC and OE bit in the backplane and local connection memory respectively. When this process is complete, the microprocessor controlling the matrices can either bring the ODE pin high or enable the OSB bit in IMS register to relinquish the high impedance state control.
Read/Write Address: Reset Value: 15
0
02H, 0000H. 11
0
14
0
13
0
12
0
10
0
9
8
7
6
5
4
3
2
BPE
1
OSB
0
SFE
BBPD BBPD BBPD LBPD LBPD LBPD LBPD 2 1 0 3 2 1 0
Bit 15-10 9-7
Name Unused BBPD2-0 Must be zero for normal operation.
Description
Backplane Block Programming Data. These bits carry the value to be loaded into the backplane connection memory block when the Memory Block Programming feature is active. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of bits BBPD2-0 are loaded into the bit 13 to bit 11 position of the backplane connection memory. Bit 15, bit 14 and bit 10 to bit 0 of the backplane connection memory are zeroed. Local Block Programming Data. These bits carry the value to be loaded into the local connection memory block when the Memory Block Programming feature is active. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of bits LBPD3-0 are loaded into the bit 15 to bit 12 position of the local connection memory. Bit 11 to bit 0 of the local connection memory low are zeroed. Bit 15 to bit 0 of local connection memory high are zeroed. Begin Block Programming Enable. A zero to one transition of this bit enables the memory block programming function. The BPE, BBPD2-0 and LBPD3-0 bits in the IMS register must be defined in the same write operation. Once the BPE bit is set high, the device requires two frames to complete the block programming. After the programming function has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort the programming operation. When BPE = 1, the other bits in the IMS register must not be changed for two frames to ensure proper operation. Table 8 - Internal Mode Selection (IMS) Register Bits
6-3
LBPD3-0
2
BPE
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Zarlink Semiconductor Inc.
Data Sheet
Read/Write Address: Reset Value: 15
0
MT90863
02H, 0000H. 11
0
14
0
13
0
12
0
10
0
9
8
7
6
5
4
3
2
BPE
1
OSB
0
SFE
BBPD BBPD BBPD LBPD LBPD LBPD LBPD 2 1 0 3 2 1 0
Bit 1
Name OSB
Description Output Stand By. This bit controls the device output drivers. OSB bit ODE pin OE bit STio0 - 31, STo0 - 15 0 0 1 High impedance state 1 0 1 Enable X 1 1 Enable X X 0 Per-channel high impedance Start Frame Evaluation. A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR register changes from zero to one, the evaluation procedure stops. Set this bit to zero for at least one frame (125s) to start another frame evaluation. Table 8 - Internal Mode Selection (IMS) Register Bits (continued)
0
SFE
Read/Write Address: Reset Value: 15
FE4
03H, 0000H. 11
FE0
14
FE3
13
FE2
12
FE1
10
CFE
9
FD9
8
FD8
7
FD7
6
FD6
5
FD5
4
FD4
3
FD3
2
FD2
1
FD1
0
FD0
Bit 15-11 10
Name FE4-0 CFE
Description Frame Evaluation Input Select. The binary value expressed in these bits refers to the frame evaluation inputs, FEi0 to FEi23. Complete Frame Evaluation. When CFE = 1, the frame evaluation is completed and bits FD9 to FD0 bits contains a valid frame alignment offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0. This bit is read-only. Frame Delay Bit 11. The falling edge of FE is sampled during the CLK-high phase (FD9 = 1) or during the CLK-low phase (FD9 = 0). This bit allows the measurement resolution to 1/2 CLK cycle. This bit is read-only. Frame Delay Bits. The binary value expressed in these bits refers to the measured input offset value. These bits are reset to zero when the SFE bit of the IMS register changes from 1 to 0. (FD8 = MSB, FD0 = LSB). These bits are also read-only Table 9 - Frame Alignment (FAR) Register Bit
9
FD9
8-0
FD8-0
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MT90863
Data Sheet
ST-BUS F0i C16i
Offset Value
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
16
FEi Input (FD[8:0] = 06H) (FD9 = 0, sample at CLK low phase)
C4i HMVIP F0i
C16i
Offset Value FEi Input
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
16
(FD[8:0] = 08H) (FD9 = 1, sample at CLK high phase)
Figure 8 - Example for Frame Alignment Measurement
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Zarlink Semiconductor Inc.
Data Sheet
MT90863
04H for DOS0 register, 05H for DOS1 register, 06H for DOS2 register, 07H for DOS3 register, 08H for DOS4 register, 09H for DOS5 register, 0000H for all DOS registers.
11 IF22 10 IF21 9 IF20 8 DLE2 7 IF12 6 IF11 5 IF10 4 DLE1 3 IF02 2 IF01 1 IF00 0 DLE0
Read/Write Address:
Reset value:
15 IF32 14 IF31 13 IF30 12 DLE3
DOS0 register
15 IF72 14 IF71 13 IF70 12 DLE7 11 IF62 10 IF61 9 IF60 8 DLE6 7 IF52 6 IF51 5 IF50 4 DLE5 3 IF42 2 IF41 1 IF40 0 DLE4
DOS1 register
15 IF112 14 IF111 13 IF110 12 DLE11 11 IF102 10 IF101 9 IF100 8 DLE10 7 IF92 6 IF91 5 IF90 4 DLE9 3 IF82 2 IF81 1 IF80 0 DLE8
DOS2 register
15 IF152 14 IF151 13 IF150 12 DLE15 11 IF142 10 IF141 9 IF140 8 DLE14 7 IF132 6 IF131 5 IF130 4 DLE13 3 IF122 2 IF121 1 IF120 0 DLE12
DOS3 register
15 IF192 14 IF191 13 IF190 12 DLE19 11 IF182 10 IF181 9 IF180 8 DLE18 7 IF172 6 IF171 5 IF170 4 DLE17 3 IF162 2 IF161 1 IF160 0 DLE16
DOS4 register
15 IF232 14 IF231 13 IF230 12 DLE23 11 IF222 10 IF221 9 IF220 8 DLE22 7 IF212 6 IF211 5 IF210 4 DLE21 3 IF202 2 IF201 1 IF200 0 DLE20
DOS5 register Name (Note 1) IFn2, IFn1, IFn0 Description Input Offset Bits 2,1 & 0. These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the STio pin: i.e., to start a new frame. The input frame offset can be selected to +4 clock periods from the point where the external frame pulse input signal is applied to the F0i inputs of the device.Figure 9 Data Latch Edge. ST-BUS mode: DLEn =0, if clock rising edge is at the 3/4 point of the bit cell. DLEn =1, if clock falling edge is at the 3/4 point of the bit cell. Table 10 - Frame Delay Offset (DOS) Register Bits
DLEn
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MT90863
Read/Write Address: 04H for DOS0 register, 05H for DOS1 register, 06H for DOS2 register, 07H for DOS3 register, 08H for DOS4 register, 09H for DOS5 register, 0000H for all DOS registers.
11 IF22 10 IF21 9 IF20 8 DLE2 7 IF12 6 IF11 5 IF10 4 DLE1 3 IF02 2 IF01 1
Data Sheet
Reset value:
15 IF32 14 IF31 13 IF30 12 DLE3
0 DLE0
IF00
DOS0 register
15 IF72 14 IF71 13 IF70 12 DLE7 11 IF62 10 IF61 9 IF60 8 DLE6 7 IF52 6 IF51 5 IF50 4 DLE5 3 IF42 2 IF41 1 IF40 0 DLE4
DOS1 register
15 IF112 14 IF111 13 IF110 12 DLE11 11 IF102 10 IF101 9 IF100 8 DLE10 7 IF92 6 IF91 5 IF90 4 DLE9 3 IF82 2 IF81 1 IF80 0 DLE8
DOS2 register
15 IF152 14 IF151 13 IF150 12 DLE15 11 IF142 10 IF141 9 IF140 8 DLE14 7 IF132 6 IF131 5 IF130 4 DLE13 3 IF122 2 IF121 1 IF120 0 DLE12
DOS3 register
15 IF192 14 IF191 13 IF190 12 DLE19 11 IF182 10 IF181 9 IF180 8 DLE18 7 IF172 6 IF171 5 IF170 4 DLE17 3 IF162 2 IF161 1 IF160 0 DLE16
DOS4 register
15 IF232 14 IF231 13 IF230 12 DLE23 11 IF222 10 IF221 9 IF220 8 DLE22 7 IF212 6 IF211 5 IF210 4 DLE21 3 IF202 2 IF201 1 IF200 0 DLE20
DOS5 register Name (Note 1)
Note 1: n denotes a STio stream number from 0 to 23.
Description
Table 10 - Frame Delay Offset (DOS) Register Bits
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Data Sheet
Measurement Result from Frame Delay Bits FD9 No clock period shift (Default) + 0.5 clock period shift +1.0 clock period shift +1.5 clock period shift +2.0 clock period shift +2.5 clock period shift +3.0 clock period shift +3.5 clock period shift +4.0 clock period shift +4.5 clock period shift 1 0 1 0 1 0 1 0 1 0 FD2 0 0 0 0 0 0 0 0 1 1 FD1 0 0 0 0 1 1 1 1 0 0 FD0 0 0 1 1 0 0 1 1 0 0 IFn2 0 0 0 0 0 0 0 0 1 1
MT90863
Corresponding Offset Bits IFn1 0 0 0 0 1 1 1 1 0 0 IFn0 0 0 1 1 0 0 1 1 0 0 DLEn 0 1 0 1 0 1 0 1 0 1
Input Stream Offset
Table 11 - Offset Bits (IFn2, IFn1, IFn0, DLEn) & Input Offset Bits (FD9, FD2-0)
ST-BUS F0i C16i STio Stream STio Stream STio Stream STio Stream
Bit 7 Bit 7 Bit 7 Bit 7
offset=0, DLE=0 offset=1, DLE=0 offset=0, DLE=1 offset=1, DLE=1 denotes the 3/4 point of the bit cell
Figure 9 - Examples for Input Offset Delay Timing
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MT90863
Data Sheet
Read/Write Address: Reset value:
15 OF15 14 OF14 13 OF13 12 OF12
0AH for FOR0 register, 0BH for FOR1 register, 0000H for all FOR registers.
11 OF11 10 OF10 9 OF09 8 OF08 7 OF07 6 OF06 5 OF05 4 OF04 3 OF03 2 OF02 1 OF01 0 OF00
FOR0 register
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 OF23 6 OF22 5 OF21 4 OF20 3 OF19 2 OF18 1 OF17 0 OF16
FOR1 register Bit 15-0 (FOR0) 7-0 (FOR1) 15-8 (FOR1) Name (Note 1) OFn Description Output Offset Bit. When 0, the first bit of the serial output stream has normal alignment with the frame pulse. When 1, the first bit of the serial output stream is advanced by 1/2 CLK cycle with respect to the frame pulse. See Figure 10 -. Must be zero for normal operation.
Unused
Note 1: n denotes a STio stream number from 0 to 23
Table 12 - Frame Output Offset (FOR) Register Bits
ST-BUS F0i C16i STio Stream STio Stream
Bit 7 Bit 7
offset=0 offset=1
HMVIP F0i HCLK C16i STo Stream STo Stream
Bit 7 Bit 7
offset=0 offset=1
denotes the starting point of the bit cell
Figure 10 - Examples for Frame Output Offset Timing
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Zarlink Semiconductor Inc.
Data Sheet
MT90863
0CH for ABR register, 0000H
11 CA6 10 CA5 9 CA4 8 CA3 7 CA2 6 CA1 5 CA0 4 SA4 3 SA3 2 SA2 1 SA1 0 SA0
Read/Write Address: Reset value:
15 0 14 CDA 13 RS 12 WS
Bit 15 14
Name unused CDA Reserved
Description
Complete Data Access. This bit is read only. This bit changes from 0 to 1 when data transfer is completed between memory and the data read register or data write register. When the RS or WS bit in this register is changed from 1 to 0, this bit is reset to zero. Read Select. A zero to one transition of this bit initiates the data transfer from memory to the data read register. This bit is reset to zero when the CDA bit changes from 0 to 1. Write Select. A zero to one transition of this bit initiates the data transfer from the data write register to memory. This bit is reset to zero when the CDA bit changes from 0 to 1. Channel Address Bits. These bits perform the same function as the external address bits when used to access various memory locations. The number (expressed in binary notation) on these bits refers to the input or output data stream channel that corresponds to the subsection of memory. Stream Address Bits. These bits perform the same function as the STA bits in the control register. The number (in binary notation) on these bits refers to the input or output data stream which corresponds to the subsection of memory. Table 13 - Address Buffer (ABR) Register Bits
13
RS
12
WS
11 - 5
CA6 - CA0
4-0
SA4 - SA0
Read/Write Address: Reset value:
15 WR15 14 WR14 13 WR13 12 WR12
0DH for DWR register, 0000H
11 WR11 10 WR10 9 WR9 8 WR8 7 WR7 6 WR6 5 WR5 4 WR4 3 WR3 2 WR2 1 WR1 0 WR0
Bit 15 - 0
Name WR15 - WR0
Description Write Data Bits. Data to be transferred to the internal memory locations. Table 14 - Data Write (DWR) Register Bits
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MT90863
Read Address: Reset value:
15 RD15 14 RD14 13 RD13 12 RD12
Data Sheet
0EH for DRR register, 0000H
11 RD11 10 RD10 9 RD9 8 RD8 7 RD7 6 RD6 5 RD5 4 RD4 3 RD3 2 RD2 1 RD1 0 RD0
Bit 15 - 0
Name RD15 - RD0
Description Read Data Bits. Data transferred from one of the internal memory locations. Table 15 - Data Read (DRR) Register Bits
15 0
14 0
13 BV/C
12 BMC
11 DC
10
9
8
7
6
5
4
3
2
1
0
BSAB BSAB BSAB BSAB BCAB BCAB BCAB BCAB BCAB BCAB BCAB 3 2 1 0 6 5 4 3 2 1 0
Bit 15,14 13
Name Unused BV/C
Description Must be zero for normal operation. Variable /Constant Throughput Delay. This bit is used to select either variable (low) or constant delay (high) modes on a per-channel basis for the local interface streams. Message Channel. When 1, the backplane connection memory contents are output on the corresponding output channel and stream. Only the lower byte (bit 7 - bit 0) will be output to the backplane interface STio pins. When 0, the local data memory address of the switched STi input channel and stream is loaded into the backplane connection memory. Directional Control. This bit enables the STio pindrivers on a per-channel basis. When 1, the STio output driver functions normally. When 0, the STio output driver is in a high-impedance state. Source Stream Address Bits. The binary value is the number of the data stream for the source of the connection. Source Channel Address Bits. The binary value identifies the channel for the connection source.
12
BMC
11
DC
10-7 (Note 1) 6-0 (Note 1)
BSAB3-0 BCAB6-0
Note 1: If bit 12 (BMC) of the corresponding backplane connection memory location is 1 (device in message mode), then these entire 8 bits (BSAB0, BCAB6 - BCAB0) are output on the output channel and stream associated with this location.
Table 16 - Blackplane Connection Memory Bits
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Zarlink Semiconductor Inc.
Data Sheet
BSAB3 to BSAB0 Bits Used to Determine the Source Stream of the connection STi0 to STi15 STi0 to STi3 STi0 to STi12
MT90863
Data Rate 2.048 Mb/s 8.192 Mb/s 2.048 Mb/s Sub-rate Switching
Table 17 - BSAB Bits Programming for Different Local Interface mode
Data Rate 2.048 Mb/s 8.192 Mb/s 2.048 Mb/s Sub-rate Switching
BCAB Bits Used to Determine the Source Channel of the Connection BCAB4 to BCAB0 (32 channel/frame) BCAB6 to BCAB0 (128 channel/frame) BCAB4 to BCAB0 (32 channel/frame) BCAB6 to BCAB0 (128 channel/frame)
Table 18 - BCAB Bits Programming for Different Data Rates
15 L/B
14 BV/C
13 BMC
12 OE
11 LSAB 4
10
9
8
7
6
5
4
3
2
1
0
LSAB LSAB LSAB LSAB LCAB LCAB LCAB LCAB LCAB LCAB LCAB 3 2 1 0 6 5 4 3 2 1 0
Bit 15
Name L/B
Description Local/Backplane Select When 1, the output channel of STo0-15 comes from STi0-15 (local) When 0, the output channel of STo0-15 comes from: STio0-31 (backplane, 2Mb/s mode) STio0-31 (backplane, 4Mb/s mode) STio0-15 (blackplane, 8Mb/s mode) STio0-23 (blackplane, HMVIP mode) Variable /Constant Throughput Delay. This bit is used to select either variable (low) or constant delay (high) modes on a per-channel basis for the source streams. Message Channel. When 1, the contents of the local connection memory are output on the corresponding output channel and stream. Only the lower byte (bit 7 - bit 0) will be output to the STo pins of the local interface. When 0, the backplane or local data memory address of the switched input channel and stream is loaded into the local connection memory. Output Enable. This bit enables the drivers of STo pins on a per-channel basis. When 1, the STo output driver functions normally. When 0, the STo output driver is in a high-impedance state. Table 19 - Local Connection Memory Low Bits
14
LV/C
13
LMC
12
OE
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MT90863
15 L/B 14 BV/C 13 BMC 12 OE 11 LSAB 4 10 9 8 7 6 5 4 3 2 1
Data Sheet
0
LSAB LSAB LSAB LSAB LCAB LCAB LCAB LCAB LCAB LCAB LCAB 3 2 1 0 6 5 4 3 2 1 0
Bit 11-7 (Note 1) 6-0 (Note 1)
Name LSAB4-0 LCAB6-0
Description Source Stream Address Bits. The binary value identifies the data stream for the source of the connection. Source Channel Address Bits. The binary value identifies the channel for the source of the connection.
Note 1: If bit 12 (LMC) of the corresponding local connection memory location is 1 (device in message mode), then these entire 8 bits (LSAB0, LCAB6 - LCAB0) are output on the output channel and stream associated with this location.
Table 19 - Local Connection Memory Low Bits (continued)
Data Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s HMVIP 2.048 Mb/s Sub-rate Switching
LSAB3 to LSAB0 Bits Used to Determine the Source Stream of the Connection STio0 to STio31 or STi0 to STi15 STio0 to STio31 STio0 to STio15 or STi0 to STi3 STio0 to STio23 STi0 to STi12
Table 20 - LSAB Bits Programming for Different Local Interface Modes
Data Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s HMVIP 2.048 Mb/s Sub-rate Switching
LCAB Bits Used to Determine the Source Channel of the Connection LCAB4 to LCAB0 (32 channel/frame) LCAB5 to LCAB0 (64 channel/frame) LCAB6 to LCAB0 (128 channel/frame) LCAB4 to LCAB0 (32 channel/frame) LCAB6 to LCAB0 (128 channel/frame) LCAB4 to LCAB0 (32 channel/frame) LCAB6 to LCAB0 (128 channel/frame)
Table 21 - LCAB Bits Programming for Different Data Rates
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Data Sheet
MT90863
15 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 LSR1
0 LSR0
Bit 15-2 (Note1) 1,0 (Note1)
Name Unused LSR1, LSR0
Description Must be zero for normal operation. Local Sub-rate Switching Bit When 11 Bit7-6 will be the output of the subrate switching stream When 10 Bit5-4 will be the output of the subrate switching stream When 01 Bit3-2 will be the output of the subrate switching stream When 00 Bit1-0 will be the output of the subrate switching stream
Note 1: If bit 12 (LMC) of the corresponding local connection memory location is 1 (device in message mode), then these entire 8 bits (Bit7-0) are output on the output channel and stream associated with this location.
Table 22 - Local Connection Memory High Bits
7.0
JTAG Support
The MT90863 JTAG interface conforms to the Boundary-Scan IEEE1149.1 standard. This stan-dard specifies a design-for-testability technique called Boundary-Scan Test (BST). The operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
7.1
Test Access Port (TAP)
The Test Access Port (TAP) accesses the MT90863 test functions. It consists of three input pins and one output pin as follows: * Test Clock Input (TCK) TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. Test Mode Select Input (TMS) The TAP Controller uses the logic signals received at the TMS input to control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to Vdd when it is not driven from an external source. Test Data Input (TDi) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to Vdd when it is not driven from an external source. Test Data Output (TDo) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo driver is set to a high impedance state. Test Reset (TRST) Reset the JTAG scan structure. This pin is internally pulled to VDD.
*
*
*
*
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MT90863
7.2 Instruction Register
Data Sheet
The MT90863 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a twobit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP Controller is in its shifted-IR state. These instructions are subsequently de-coded to achieve two basic functions: to select the test data register that may operate while the instruction is current; and, to define the serial test data register path that is used to shift data between TDi and DO during data register scan-ning.
7.3
*
Test Data Register
As specified in IEEE 1149.1, the MT90863 JTAG Interface contains three test data registers: The Boundary-Scan Register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the MT90863 core logic. The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDi to its TDo. The Device Identification Register The device identification register is a 32-bit register. The register contents are: MSB LSB
* *
0000 0000 1000 0110 0011 0001 0100 1011 The LSB bit in the device identification register is the first bit clock out. The MT90863 scan register contains 212 bits. Bit 0 in Table 23 Boundary Scan Register is the first bit clocked out. All tri-state enable bits are active high.
Boundary Scan Bit 0 to Bit 213 Device Pin Tri-state Control Output Scan Cell Input Scan Cell 0 1 2 3 4 5 6 7 8 9 10
A0 A1 A2 A3 A4 A5 A6 A7 DS R/W CS
Table 23 - Boundary Scan Register Bits
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Zarlink Semiconductor Inc.
Data Sheet
Boundary Scan Bit 0 to Bit 213 Device Pin Tri-state Control 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 Output Scan Cell 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 109 110 111 112 114 113 115 Input Scan Cell 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58
MT90863
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DTA STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 ODE STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 STo9 STo10 STo11 STo12 STo13 STo14 STo15 C16i F0i C4i/C8i F0o C4o
Table 23 - Boundary Scan Register Bits (continued)
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MT90863
Boundary Scan Bit 0 to Bit 213 Device Pin Tri-state Control 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 194 197 200 203 206 209 Output Scan Cell 117 120 123 126 129 132 135 138 141 144 147 150 153 156 159 162 165 168 171 174 177 180 183 186 189 192 195 198 201 204 207 210 Input Scan Cell 118 121 124 127 130 133 136 139 142 145 148 151 154 157 160 163 166 169 172 175 178 181 184 187 190 193 196 199 202 205 208 211 212
Data Sheet
STio0/FE0 STio1/FE1 STio2/FE2 STio3/FE3 STio4/FE4 STio5/FE5 STio6/FE6 STio7/FE7 STio8/FE8 STio9/FE9 STio10/FE10 STio11/FE11 STio12/FE12 STio13/FE13 STio14/FE14 STio15/FE15 STio16/FE16 STio17/FE17 STio18/FE18 STio19/FE19 STio20/FE20 STio21/FE21 STio22/FE22 STio23/FE23 STio24 STio25 STio26 STio27 STio28 STio29 STio30 STio31 RESET
Table 23 - Boundary Scan Register Bits (continued)
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Data Sheet Absolute Maximum Ratings*
Parameter 1 2 3 4 Supply Voltage Input Voltage Output Voltage Package power dissipation Symbol VDD VI Vo PD Min -0.5 -0.5 -0.5 Max 5.0
MT90863
Units V V V W C
VDD +0.5 VDD +0.5 2
5 Storage temperature TS - 55 +125 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics 1 2 3 4 5 Operating Temperature Positive Supply Input High Voltage Input High Voltage on 5V Tolerant Inputs Input Low Voltage Sym TOP VDD VIH VIH VIL VSS Min -40 3.0 0.7VDD Typ Max +85 3.6 VDD 5.5 0.3VDD Units C V V V V Test Conditions
AC Electrical Characteristics - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8
O U T P U T S I N P U T S
Sym IDD VIH VIL IIL IBL CI VOH VOL IOZ
Min 0.7VDD
Typ 52
Max 85 0.3VDD 10 50 10
Units mA V V A A pF V
Test Conditions Output unloaded
Supply Current Input High Voltage Input Low Voltage Input Leakage (input pins) Input Leakage (bi-directional pins) Input Pin Capacitance Output High Voltage Output Low Voltage High Impedance Leakage
00.8VDD 0.4 5
V A pF
10 9 Output Pin Capacitance CO Note: 1. Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V)
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
Characteristics 1 2 CMOS Threshold Rise/Fall Threshold Voltage High Sym VCT VHM Level 0.5VDD 0.7VDD Units V V Conditions
0.3VDD V 3 Rise/Fall Threshold Voltage Low VLM * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied
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MT90863
AC Electrical Characteristics - Frame Pulse and CLK
Characteristic 1 2 3 4 5 6 7 8 9 Frame pulse width Frame Pulse Setup time before C16i falling Frame Pulse Hold Time from C16i falling C16i Period C16i Pulse Width High C16i Pulse Width Low Clock Rise/Fall Time FPo Frame pulse output width FPo Frame Pulse output setup time before C4o falling Sym
tFPW tFPS tFPH tCP tCH tCL tr, tf tFPOW tFPOS tFPOH tC4OP tC40H tC40L tCFPW tCFPS tCFPH tHCP tHCH tHCL tHFPW tHFPS tHFPH tHCP tHCH tHCL tHr, tHf tDIF tDC4O
Data Sheet
Min
Typ 60 10 10 60 30 30 10 244
Max
Units ns ns ns ns ns ns ns ns
Notes ST-BUS mode
ST-BUS, CT Bus or HMVIP mode
10 20 10 244 122 122 122 45 45 122 61 61 244 50 50 244 122 122 10 -10 -10
150 150
ns ns ns ns ns ns CT Bus mode
10 FPo Frame Pulse output Hold Time from C4o falling 11 C4o Period 12 C4o Pulse Width High 13 C4o Pulse Width Low 14 CT frame pulse width 15 CT Frame Pulse Setup Time before C8i rising 16 CT Frame Pulse Hold Time from C8i rising 17 C8i Period 18 C8i Pulse Width High 19 C8i Pulse Width Low 20 HMVIP frame pulse width 21 Frame Pulse Setup Time before C4i falling 22 Frame Pulse Hold Time from C4i falling 23 C4i Period 24 C4i Pulse Width High 25 C4i Pulse Width Low 26 C4i/C8i Rise/Fall Time 27 Delay between falling edge of C4i/C8i and rising edge of C16i 28 Delay between falling edge of C16i and falling edge of C4o
90 90
ns ns ns ns ns ns HMVIP mode
150 150
ns ns ns ns ns ns HMVIP or CT Bus mode
10 10
ns ns
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Data Sheet
MT90863
AC Electrical Characteristics - Serial Streams for Backplane and Local Interfaces
Characteristic 1 2 3 4 5 STio/STi Set-up Time STio/STi Hold Time STo Delay - Active to Active STo delay - Active to High-Z - High-Z to Active Sym
tSIS tSIH tSOD
Min 0 6 5
Typ
Max
Units ns ns
Test Conditions
16
32 35 35
ns ns ns
CL=200pF RL=1K, CL=200pF, See Note 1
tZD tODE
Output Driver Enable (ODE) Delay
Note: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
tFPiW F0i tFPiS tFPiH C16i 16.384MHz F0o C4o 4.096MHz tFPoS tCP tCH tCL VTT tr VTT tFPoW tFPoH tC4L tDC4o tSOD8 STo/STio (8Mb/s) output STi/STio (8Mb/s) input STio (4Mb/s) output STio (4Mb/s) input STo/STio (2Mb/s) output STi/STio (2Mb/s) input
Bit 1, Ch 127 Bit 0, Ch 127 Bit 7, Ch 0
tf tC4P tC4H VTT VHM VTT VLM VTT VTT VTT VTT
tr
Bit 6, Ch 0 Bit 5, Ch 0
tf
Bit 4, Ch 0
tSIS8
Bit 1, Ch 127 Bit 0, Ch 127 Bit 7, Ch 0
tSIH8
Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0
tSOD4
Bit 0, Ch63 Bit 7, Ch 0 Bit 6, Ch 0
tSIS4
Bit 0, Ch 63 Bit 7, Ch 0
tSIH4
Bit 6, Ch 0
tSOD2
Bit 0, Ch 31 Bit 7, Ch 0 Bit 6, Ch 0
VTT VTT
tSIS2
Bit 0, Ch 31 Bit 7, Ch 0
tSIH2
Figure 11 - ST-BUS Timing for Stream rate of 2.048, 4.096 or 8.192 Mb/s
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MT90863
tCFPW F0i tCFPS C16i 16.384MHz C4i/C8i 8.192MHz tCFPH tCP tCH tCL tr
Data Sheet
VTT VTT tC8P tFPoW tC8H tr tf tC8L tC4P tf VTT tf VTT tC4L tC4H VHM VTT VLM tf
Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0
F0o
C4o 4.096MHz
tDC4o tSOD8
tr
ST0/STio (8Mb/s) output STi/STio (8Mb/s) input STio (4Mb/s) output STio (4Mb/s) input
Bit 1, Ch 127
Bit 0, Ch 127
Bit 7, Ch 0
VTT
tSIS8
Bit 1, Ch 127 Bit 0, Ch 127 Bit 7, Ch 0
tSIH8
Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0
VTT
tSOD4
Bit 0, Ch63 Bit 7, Ch 0 Bit 6, Ch 0
VTT
tSIS4
Bit 0, Ch 63 Bit 7, Ch 0
tSIH4
Bit 6, Ch 0
VTT
tSOD2 STo/STio (2Mb/s) output STi/STio (2Mb/s) input
Bit 0, Ch 31 Bit 7, Ch 0 Bit 6, Ch 0
VTT
tSIS2
Bit 0, Ch 31 Bit 7, Ch 0
tSIH2 VTT
Figure 12 - CT Bus Timing for Stream rate of 2.048, 4.096 or 8.192 Mb/s
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Zarlink Semiconductor Inc.
Data Sheet
MT90863
tHFPS F0i tHCL tHCP tHCH
VHM VTT VLM
tHFPW
tHFPH VTT
C4i/C8i 4.096MHz
t tDC4oDIF
tHr tCP
tCH
tHf
tCL
tr VTT
C16i 16.384MHz tFPoS F0o tC4L C4o 4.096MHz tDC4o tSOD8 STio (8Mb/s) output STio (8Mb/s) input STio (2Mb/s) output STio (2Mb/s) input
Bit 1, Ch 127 Bit 0, Ch 127 Bit 7, Ch 0
tFPoW
tFPoH tC4P tC4H
tC8L tf VTT VHM VTT VLM
tr
tf
Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0
VTT
tSIS8
Bit 1, Ch 127 Bit 0, Ch 127 Bit 7, Ch 0
tSIH8
Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0
VTT
tSOD2
Bit 0, Ch 31 Bit 7, Ch 0 Bit 6, Ch 0
VTT
tSIS2
Bit 0, Ch 31 Bit 7, Ch 0
tSIH2 VTT
Figure 13 - HMVIP Bus Timing for Stream rate of 2.048 Mb/s or 8.192 Mb/s
CLK tDZ STo Valid Data tZD STo HiZ
VTT
HiZ
VTT
Valid Data
VTT
Figure 14 - Serial Output and External Control
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MT90863
Data Sheet
ODE tODE STo HiZ tODE
VTT
Valid Data
HiZ
VTT
Figure 15 - Output Driver Enable (ODE)
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode
Characteristics 1 2 3 4 5 6 7 CS setup from DS falling R/W setup from DS falling Address setup from DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Data setup from DTA low on read Reading registers Reading Memory Data hold on read Sym tCSS tRWS tADS tCSH tRWH tADH tDDR_REG tDDR_MEM tDHR 10 10 6 16 440 11 ns Min Typ 0 10 5 Max Units ns ns ns ns ns ns ns CL=50pF Test Conditions
8
CL=50pF, RL=1K Note 1
9
Data setup on write (fast write)
tDSW_REG tSWD tDHW tAKD_REG tAKD_MEM tAKH 5
2 150
ns ns ns ns CL=50pF
10 Valid data delay on write (slow write) 11 Data hold on write 12 Acknowledgment delay: Reading/writing registers Reading/writing memory 13 Acknowledgment hold time
40 470 17 ns
CL=50pF, RL=1K, Note
Note: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
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Data Sheet
MT90863
VTT VTT tRWS tRWH VTT tADS tADH
VALID ADDRESS
DS
tCSS
tCSH
CS
R/W
A0-A7
VTT tDHR
D0-D15 READ tSWD D0-D15 WRITE
VALID READ DATA
VTT tDHW VTT
tDSW
VALID WRITE DATA
tDDR tAKD VTT tAKH
DTA
Figure 16 - Motorola Non-Multiplexed Bus Timing
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MT90863
Data Sheet
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c Zarlink Semiconductor 2002 All rights reserved.
Package Code : GA Previous package codes:
ISSUE ACN DATE APPRD.
1 213935 20Jan03
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